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| 74VHCT00A Quad 2-Input NAND Gate July 1997 Revised February 2005 74VHCT00A Quad 2-Input NAND Gate General Description The VHCT00A is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages, including buffer output, which provide high noise immunity and stable output. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Features High speed: tPD 5.0 ns (typ) at TA 2.0V, VIL 25qC 0.8V High noise immunity: VIH Power down protection is provided on all inputs and outputs Low noise: VOLP 0.8V (max) 25qC Low power dissipation: ICC 2 PA (max) at TA Pin and function compatible with 74HCT00 Ordering Code: Order Number 74VHCT00AM 74VHCT00ASJ 74VHCT00AMTC 74VHCT00AMTCX_NL (Note 1) 74VHCT00AN 74VHCT00AN_NL (Note 1) Package Number M14A M14D MTC14 MTC14 N14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device. (c) 2005 Fairchild Semiconductor Corporation DS500023 www.fairchildsemi.com 74VHCT00A Logic Symbol Connection Diagram Pin Descriptions Pin Names An, Bn On Description Inputs Outputs Truth Table A L L H H B L H L H O H H H L www.fairchildsemi.com 2 74VHCT00A Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Recommended Operating Conditions (Note 6) Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) (Note 3) (Note 4) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: VCC 0V. Note 5: VOUT GND, V OUT ! VCC (Outputs Active) Note 6: Unused inputs must be held HIGH or LOW. They may not float. 4.5V to 5.5V 0V to 5.5V 0V to VCC 0V to 5.5V 40qC to 85qC DC Electrical Characteristics Symbol VIH VIL VOH VOL IIN ICC ICCT IOFF Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Quiescent Supply Current Maximum ICC/ Input Output Leakage Current (Power Down State) VCC (V) 4.5 5.5 4.5 5.5 4.5 4.5 4.5 4.5 0 5.5 5.5 5.5 0.0 4.40 3.94 0.0 0.1 0.36 4.50 TA Min 2.0 2.0 0.8 0.8 4.40 3.80 0.1 0.44 25qC Typ Max TA 40qC to 85qC Max 2.0 2.0 0.8 0.8 Min Units V V V V V V VIN VIN VIN VIN VIN VOUT Conditions VIH VIH IOH IOH IOL IOL 50 PA 8 mA 50 PA 8 mA or VIL or VIL r0.1 2.0 1.35 0.5 r1.0 20.0 1.50 5.0 PA PA mA 5.5V or GND VCC or GND 3.4V VCC or GND 5.5V Other Inputs PA Noise Characteristics Symbol VOLP (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA Typ 0.4 25qC Limit 0.8 Units V V V V CL CL CL CL Conditions 50 pF 50 pF 50 pF 50 pF 0.4 0.8 2.0 0.8 Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT00A AC Electrical Characteristics Symbol tPLH tPHL CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Propagation Delay VCC (V) 5.0 r 0.5 TA Min 25qC Typ 5.0 5.5 4 17 Max 6.9 7.9 10 TA 40qC to 85qC Max 8.0 9.0 10 1.0 1.0 Min Units ns pF pF CL CL VCC Conditions 15 pF 50 pF Open (Note 8) Note 8: CPD is defined as the value of the internal equivalent capacitance, which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN I CC/4 (per gate) www.fairchildsemi.com 4 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHCT00A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHCT00A Quad 2-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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